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Special Pins

Omega2 devices have special pins that require consideration at design time:

  • System boot pins that affect the boot sequence
  • SPI pins used by onboard flash
  • GPIOs that control the Omega LED and Reset pins
  • Other pins of note

System boot pins

There are seven pins that affect the Omega’s boot sequence and require special attention. The pins fall into two categories:


These pins must be floating at boot time. They cannot be pulled up or pulled down, or else the Omega will not boot.

Floating or pulled down:

These pins must be floating or pulled down at boot time. They cannot be pulled up during the boot sequence or else the Omega will not boot.

Once the Omega device has been booted, these pins can be used normally.

GPIODescriptionBoot Time
GPIO1GPIO / I2S SDOMust be floating or pulled down
GPIO6SPI CS1/ GPIOMust be floating
GPIO7SPI CLKMust be floating
GPIO8SPI MOSIMust be floating
GPIO12UART TX0Must be floating or pulled down
GPIO45UART TX1 / GPIOMust be floating
GPIO36GPIO / PERST_N (Omega2S Only)Must be floating

SPI pins

The Omega’s processor communicates with the onboard SPI flash storage using Chip Select 0 on the Omega’s SPI bus. Since there are two SPI chip select signals it’s possible to connect an additional SPI device to the Omega using Chip Select 1. As such, the SPI communication pins - CLK, MOSI, and MISO - are exposed on the Omega2's expansion header as GPIOs 7, 8, and 9.

Since the Omega’s storage uses SPI, the SPI communication pins - GPIOs 7, 8, and 9 - must be used for the SPI protocol and cannot be used as regular GPIOs. These GPIOs are reserved for SPI devices and will use Chip Select 1, on GPIO6, as their chip select signal on the Omega’s SPI bus.

SPI CS1I/OSPI Chip Select 1
SPI_CLKOSPI Clock (Cannot be used as a regular GPIO)
SPI_MISOISPI Master Input/Slave Output(Cannot be used as a regular GPIO)
SPI_MOSIOSPI Master Output/Slave Input (Cannot be used as a regular GPIO)
SPI_CS0OSPI Chip Select 0. Only exposed on Omega2S. (Cannot be used as a regular GPIO)

Imortant Notes:

  • GPIOs 7, 8, and 9 can only be used for the SPI bus and cannot be used as regular GPIOs.
    • Connecting non-SPI circuitry to these pins may prevent your Omega from booting or could damage the device.
  • The SPI CS1 pin, GPIO 6, may be used to control an additional external SPI device.
  • The SPI CS1 pin, GPIO 6, may still be used as a regular GPIO when configured as a GPIO using omega2-ctrl.

For more information on GPIOs and Pins, see the pin multiplexing article.

Reset pins

The Omega’s hardware design uses dedicated GPIOs to control the Omega’s LED and accept an incoming Reset signal:

GPIO38 / SW_RSTI/OFW_RST Active-High

Soft reset

The GPIO38 pin acts as the soft reset on the Omega2. It is configured in the Onion Omega2 firmware to be the programmable user input button. By default, the input is configured active-high and will trigger a reboot of the operating system.

Hard reset

The HW_RST_N pin acts as the hard reset on the Omega2S. This input is active-low, and, when asserted low, will perform a hard reset (a power cycle) of the CPU.

Special reboot considerations when using HW_RST_N

Both the Omega2+ CPU and the Flash memory boot from a 3 byte address mode. During a reboot the Flash memory and CPU upgrade to a 4 byte address mode to access higher memory addresses.

During an unexpected reset (brownout) the CPU resets, but the memory remains in the 4 Byte address mode. This mismatch prevents the CPU from booting normally. A hard reset (power cycle) will reset the Flash memory back to a 3 Byte address mode and the system will boot normally.

Different boot conditions
Boot StateGPIO 6 (SPI CS1) StateCPU address modeFlash address modeBoot Result
Cold bootDefault (pull down)3 Byte3 ByteSuccess
Hot bootDefault (pull down)3 Byte4 ByteFail
Cold bootPull up4 Byte3 ByteFail
Hot bootPull up4 Byte4 ByteSuccess

GPIO6 & GPIO11 HW_RST_N requirements

Based on the table above, we need to have the GPIO 6 pulled down during a cold boot and pulled up during a hot boot, for the system to boot successfully. The following circuit does just that.


  • During a cold boot, GPIO 11 starts as LOW and GPIO 6 reads LOW.
  • During a normal boot, the boot loader sets GPIO 11 to HIGH, which charges the capacitor to 3.3V.
  • During an unexpected reset or hot boot, the capacitor temporarily pulls GPIO 6 to HIGH, setting the CPU to boot from a 4 Byte address mode.

LED pins

The Omega uses a dedicated GPIO to control the status LED:

GPIOFunctionOmega2/Omega2+Omega2S Pin Number
GPIO44Omega Status LEDNo, connected to onboard LED19

Differences between Omega2/2+ vs Omega2S/2S+

  • On the Omega2/Omega2+, the pin is not exposed but directly connected to an onboard LED.
  • On the Omega2S/2S+, the pin is exposed.

Pin behavior during boot

Omegas’a bootloader governs pin behavior. Most of Omega’s pins will remain at the default digital low state during the boot process. There is one pin that behaves differently. The GPIO 11 pin will settle at digital high. Previously, this pin provided power for the reset button on the Omega docks.

GPIO11Will settle at Digital High - Previously used to provide power for the reset button on Omega2 Docks

The Omega2 bootloader is open source and can be found on GitHub: OnionIoT/omega2-bootloader.